1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit, and more particularly, to a data output apparatus.
2. Related Art
In mobile semiconductor memory devices, the need for low power consumption and high speed operation has increased. Accordingly, it is necessary to design a semiconductor integrated circuit that satisfies low power consumption and high speed operation characteristics. Among apparatuses composing a semiconductor integrated circuit, a data output apparatus is a device that has significant influences on power consumption and operation speed.
FIG. 1 is a schematic circuit diagram of a conventional data output apparatus. In FIG. 1, a data output apparatus 1 includes an inverter IV1, a NAND gate ND1, a NOR gate NR1, a first transistor M1, and a second transistor M2. In addition, a semiconductor integrated circuit includes a plurality of data input/output pads DQ functioning as output terminals to output data. Accordingly, when a data output enable signal ‘DOUT_EN’ is enabled to a logical high level, the NAND gate ND1 and the NOR gate NR1 operate as an inverter, respectively. Here, the data output enable signal ‘DOUT_EN’ is a signal that is enabled to a logical high level according to a read operation.
A pull-up driver, i.e., the first transistor M1 drives the pad DQ to a level of power supply voltage source VDDQ when an input data signal ‘DATA’ is at a logical high level. On the contrary, a pull-down driver, i.e., the second transistor M2, drives the pad DQ to a level of ground voltage source VSSQ when the input data signal ‘DATA’ is at a logical low level.
As shown in FIG. 1, the data output apparatus 1 is designed such that output data swings between a level of power supply voltage VDDQ and a level of ground voltage VSSQ, and it has no additional circuit for termination function. Here, the termination function has an effect to improve data transmission speed to restrict a swing range of data in order to improve data transmission speed. However, the termination function increases power consumption. Thus, a data output apparatus has no additional circuit construction for termination function.
FIG. 2 is a waveform demonstrating output data of the apparatus of FIG. 1. In FIG. 2, it may happen that a level of power supply voltage source VDDQ deviates from a predetermined level due to noise. In this case, data output from a data output apparatus may also include a noise component, such as region A of FIG. 2. As a result, the data output apparatus 1 (in FIG. 1) is problematic.
First, since the data output apparatus 1 has no termination function, there is a problem that data transmission speed is degraded. When a circuit construction for termination function is added, data transmission speed may be improved, but power consumption increases. Accordingly, the data output apparatus 1 has a difficulty in simultaneously satisfying low power consumption and high speed operation requirements.
Second, when a power supply voltage source VDDQ abnormally varies, a level of data output from the data output apparatus 1 (in FIG. 1) becomes unstable. Accordingly, an operation error may be caused in a system that receives the data output from the data output apparatus 1.